As known, in non-volatile, floating gate memory cells, writing a cell modifies the quantity of electric charges stored in the floating gate region of the cell, thus programming the cell threshold voltage according to analog or digital values to be stored.
Analog non-volatile memory cells are typically read through a reading device formed by an analog/digital (A/D) converter. Such A/D converters have a plurality of comparator circuits, each receiving at a first input a voltage correlated to the value of the current flowing in the read memory cell, and thus to the value of the cell threshold voltage, and at a second input a reference voltage having a predetermined reference value. The comparator circuits then generate at the output respective digital signals, each of which has a high or low logic state indicative of the outcome of the comparison. The comparator circuit output signals are then supplied to a decoding circuit that, according to the logic state of the output signals of the comparator circuits, generates at the output a binary word associated with the threshold voltage of the read memory cell.
It is also known that during programming, the memory cell is verified to ensure that the required datum is stored. Verifying of a memory cell must be carried out with much greater accuracy than during normal reading of the cell ensure long term legibility of the cell and correctness of the stored datum.
Thus, during program and verify, it is typically necessary to generate binary words correlated to the threshold voltage of the read memory cells and have a bit number larger than that required during normal reading operations. Consequently, the circuit architecture of reading devices of the above-described type, comprising 2.sup.n -1 comparator circuits for binary words of n bits, makes it difficult to use a single reading device both for verify and memory cell reading.